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A low latency and low power indirect topology for on-chip communication.
PLoS One. 2019 Oct 2;14(10):e0222759. doi: 10.1371/journal.pone.0222759. eCollection 2019.
PLoS One. 2019.
PMID: 31577809
Free PMC article.
A New Cross-By-Pass-Torus Architecture Based on CBP-Mesh and Torus Interconnection for On-Chip Communication.
Gulzari UA, Sajid M, Anjum S, Agha S, Torres FS.
Gulzari UA, et al.
PLoS One. 2016 Dec 1;11(12):e0167590. doi: 10.1371/journal.pone.0167590. eCollection 2016.
PLoS One. 2016.
PMID: 27907147
Free PMC article.
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