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Large-Area CVD-Grown Sub-2 V ReS2 Transistors and Logic Gates.
Dathbun A, Kim Y, Kim S, Yoo Y, Kang MS, Lee C, Cho JH. Dathbun A, et al. Among authors: kim s, kim y. Nano Lett. 2017 May 10;17(5):2999-3005. doi: 10.1021/acs.nanolett.7b00315. Epub 2017 Apr 24. Nano Lett. 2017. PMID: 28414455
Selectively Metallized 2D Materials for Simple Logic Devices.
Dathbun A, Kim Y, Choi Y, Sun J, Kim S, Kang B, Kang MS, Hwang DK, Lee S, Lee C, Cho JH. Dathbun A, et al. Among authors: kim s, kim y. ACS Appl Mater Interfaces. 2019 May 22;11(20):18571-18579. doi: 10.1021/acsami.9b03078. Epub 2019 May 13. ACS Appl Mater Interfaces. 2019. PMID: 31017757
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