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Low power, less occupying area, and improved speed of a 4-bit router/rerouter circuit for low-density parity-check (LDPC) decoders.
F1000Res. 2022 Jan 5;11:7. doi: 10.12688/f1000research.73404.2. eCollection 2022.
F1000Res. 2022.
PMID: 36451662
Free PMC article.
Design of a Sub-Picosecond Jitter with Adjustable-Range CMOS Delay-Locked Loop for High-Speed and Low-Power Applications.
Abdulrazzaq BI, Ibrahim OJ, Kawahito S, Sidek RM, Shafie S, Yunus NA, Lee L, Halin IA.
Abdulrazzaq BI, et al. Among authors: lee l.
Sensors (Basel). 2016 Sep 28;16(10):1593. doi: 10.3390/s16101593.
Sensors (Basel). 2016.
PMID: 27690040
Free PMC article.
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