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Page 1
Effect of Contact Plug Deposition Conditions on Junction Leakage and Contact Resistance in Multilevel CMOS Logic Interconnection Device.
Micromachines (Basel). 2020 Feb 6;11(2):170. doi: 10.3390/mi11020170.
Micromachines (Basel). 2020.
PMID: 32041270
Free PMC article.
Process Optimization of Via Plug Multilevel Interconnections in CMOS Logic Devices.
Cui Y, Jeong JY, Gao Y, Pyo SG.
Cui Y, et al. Among authors: jeong jy.
Micromachines (Basel). 2019 Dec 25;11(1):32. doi: 10.3390/mi11010032.
Micromachines (Basel). 2019.
PMID: 31881782
Free PMC article.
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