A board system for high-speed image analysis and neural networks

E Sackinger; H P Graf

doi:10.1109/72.478407

A board system for high-speed image analysis and neural networks

IEEE Trans Neural Netw. 1996;7(1):214-21. doi: 10.1109/72.478407.

Authors

E Sackinger¹, H P Graf

Affiliation

¹ ATandT Bell Labs., Holmdel, NJ.

PMID: 18255573
DOI: 10.1109/72.478407

Abstract

Two ANNA neural-network chips are integrated on a 6U VME board, to serve as a high-speed platform for a wide variety of algorithms used in neural-network applications as well as in image analysis. The system can implement neural networks of variable sizes and architectures, but can also be used for filtering and feature extraction tasks that are based on convolutions. The board contains a controller implemented with field programmable gate arrays (FPGA's), memory, and bus interfaces, all designed to support the high compute power of the ANNA chips. This new system is designed for maximum speed and is roughly 10 times faster than a previous board. The system has been tested for such tasks as text location, character recognition, and noise removal as well as for emulating cellular neural networks (CNN's). A sustained speed of up to two billion connections per second (GC/s) and a recognition speed of 1000 characters per second has been measured.