Two-dimensional transition metal dichalcogenides (TMDCs) have natural advantages in overcoming the short-channel effect in field-effect transistors (FETs) and in fabricating three-dimensional FETs, which benefit in increasing device density. However, so far, most reported works related to MoS2 FETs with a sub-100 nm channel employ mechanically exfoliated materials and all of the works involve electron beam lithography (EBL), which may limit their application in fabricating wafer-scale device arrays as demanded in integrated circuits (ICs). In this work, MoS2 FET arrays with a side-wall source and drain electrodes vertically distributed are designed and fabricated. The channel length of the as-fabricated FET is basically determined by the thickness of an insulating layer between the source and drain electrodes. The vertically distributed source and drain electrodes enable to reduce the electrode-occupied area and increase in the device density. The as-fabricated vertical FETs exhibit on/off ratios comparable to those of mechanically exfoliated MoS2 FETs with a nanoscale channel length under identical VDS. In addition, the as-fabricated FETs can work at a VDS as low as 10 mV with a desirable on/off ratio (1.9 × 107), which benefits in developing low-power devices. Moreover, the fabrication process is free from EBL and can be applied to wafer-scale device arrays. The statistical results show that the fabricated FET arrays have a device yield of 87.5% and an average on/off ratio of about 1.7 × 106 at a VDS of 10 mV, with the lowest and highest ones to be about 1.3 × 104 and 1.9 × 107, respectively, demonstrating the good reliability of our fabrication process. Our work promises a bright future for TMDCs in realizing high-density and low-power nanoelectronic devices in ICs.
Keywords: 3D architecture; FET arrays; MoS2 FET; nanoscale channel length; vertical FET.