Steep-slope vertical-transport transistors built from sub-5 nm Thin van der Waals heterostructures

Qiyu Yang; Zheng-Dong Luo; Huali Duan; Xuetao Gan; Dawei Zhang; Yuewen Li; Dongxin Tan; Jan Seidel; Wenchao Chen; Yan Liu; Yue Hao; Genquan Han

doi:10.1038/s41467-024-45482-x

Steep-slope vertical-transport transistors built from sub-5 nm Thin van der Waals heterostructures

Nat Commun. 2024 Feb 7;15(1):1138. doi: 10.1038/s41467-024-45482-x.

Authors

Qiyu Yang¹, Zheng-Dong Luo^{2

3}, Huali Duan⁴, Xuetao Gan⁵, Dawei Zhang^{6

7}, Yuewen Li⁸, Dongxin Tan¹, Jan Seidel^{6

7}, Wenchao Chen⁴, Yan Liu^{9

10}, Yue Hao¹, Genquan Han^{1

8}

Affiliations

¹ State Key Discipline Laboratory of Wide Band Gap Semiconductor Technology, School of Microelectronics, Xidian University, Xi'an, 710071, China.
² State Key Discipline Laboratory of Wide Band Gap Semiconductor Technology, School of Microelectronics, Xidian University, Xi'an, 710071, China. zhdluo@xidian.edu.cn.
³ Hangzhou Institute of Technology, Xidian University, Hangzhou, 311200, China. zhdluo@xidian.edu.cn.
⁴ ZJU-UIUC Institute, International Campus, Zhejiang University, Haining, 314400, China.
⁵ Key Laboratory of Light Field Manipulation and Information Acquisition, Ministry of Industry and Information Technology, and Shaanxi Key Laboratory of Optical Information Technology, School of Physical Science and Technology, Northwestern Polytechnical University, Xi'an, 710129, China. xuetaogan@nwpu.edu.cn.
⁶ School of Materials Science and Engineering, UNSW Sydney, Sydney, NSW 2052, Australia.
⁷ ARC Centre of Excellence in Future Low-Energy Electronics Technologies (FLEET), UNSW Sydney, Sydney, NSW 2052, Australia.
⁸ Hangzhou Institute of Technology, Xidian University, Hangzhou, 311200, China.
⁹ State Key Discipline Laboratory of Wide Band Gap Semiconductor Technology, School of Microelectronics, Xidian University, Xi'an, 710071, China. xdliuyan@xidian.edu.cn.
¹⁰ Hangzhou Institute of Technology, Xidian University, Hangzhou, 311200, China. xdliuyan@xidian.edu.cn.

Abstract

Two-dimensional (2D) semiconductor-based vertical-transport field-effect transistors (VTFETs) - in which the current flows perpendicularly to the substrate surface direction - are in the drive to surmount the stringent downscaling constraints faced by the conventional planar FETs. However, low-power device operation with a sub-60 mV/dec subthreshold swing (SS) at room temperature along with an ultra-scaled channel length remains challenging for 2D semiconductor-based VTFETs. Here, we report steep-slope VTFETs that combine a gate-controllable van der Waals heterojunction and a metal-filamentary threshold switch (TS), featuring a vertical transport channel thinner than 5 nm and sub-thermionic turn-on characteristics. The integrated TS-VTFETs were realised with efficient current switching behaviours, exhibiting a current modulation ratio exceeding 1 × 10⁸ and an average sub-60 mV/dec SS over 6 decades of drain current. The proposed TS-VTFETs with excellent area- and energy-efficiency could help to tackle the performance degradation-device downscaling dilemma faced by logic transistor technologies.

Abstract

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