The future of Moore's Law for high-performance integrated circuits (ICs) is going to be driven more by advanced packaging and three-dimensional (3D) integration than by simply decreasing transistor size. 3D ICs offer low-power consumption, high-performance and a smaller footprint compared to conventional 2D ICs. The key enabling technology to 3D integration is the interposer that provides interconnects to route signals between the chiplets that comprise the IC. However, the fabrication of high-aspect ratio through wafer vias (TWVs), that provide electrical and mechanical connection between chiplets on the top and bottom of the interposer, is one of the important challenges that limit interposer performance. Current fabrication technologies are limited by tapering effects and the need for direct line of sight to the fabrication surface. These limit the possible aspect ratios of vias and require large, complicated surface traces to connect the vias to the chiplets. Here, we demonstrate the fabrication of high-aspect ratio, non-line-of-sight TWVs in silicon carbide (SiC). SiC provides better mechanical, chemical, and thermal performance than silicon (Si). The technique uses an electro-chemical etch process that utilizes two-photon absorption to create any arbitrary 3D structure in SiC allowing for direct, subsurface routing between chiplets.
© 2024. The Author(s).