A synaptic device with a multilayer structure is proposed to reduce the operating power of neuromorphic computing systems while maintaining a high-density integration. A simple metal-insulator-metal (MIM)-structured multilayer synaptic device is developed using an 8-inch wafer-based and complementary metal-oxide-semiconductor (CMOS) fabrication process. The three types of MIM-structured synaptic devices are compared to assess their effects on reducing the operating power. The obtained results exhibited low-power operation owing to the inserted layers acting as an internal resistor. The modulated operational conductance level and simple MIM structure demonstrate the feasibility of implementing both low-power operation and high-density integration in multilayer synaptic devices.
Keywords: CMOS compatibility; MIM structure; inner resistor effect; low-power operation; multilayer synaptic device.