Silicon-van der Waals heterointegration for CMOS-compatible logic-in-memory design

Mu-Pai Lee; Caifang Gao; Meng-Yu Tsai; Che-Yi Lin; Feng-Shou Yang; Hsin-Ya Sung; Chi Zhang; Wenwu Li; Jun Li; Jianhua Zhang; Kenji Watanabe; Takashi Taniguchi; Keiji Ueno; Kazuhito Tsukagoshi; Ching-Hwa Ho; Junhao Chu; Po-Wen Chiu; Mengjiao Li; Wen-Wei Wu; Yen-Fu Lin

doi:10.1126/sciadv.adk1597

Silicon-van der Waals heterointegration for CMOS-compatible logic-in-memory design

Sci Adv. 2023 Dec 8;9(49):eadk1597. doi: 10.1126/sciadv.adk1597. Epub 2023 Dec 8.

Authors

Mu-Pai Lee¹, Caifang Gao², Meng-Yu Tsai^{3

4}, Che-Yi Lin³, Feng-Shou Yang³, Hsin-Ya Sung¹, Chi Zhang^{2

5}, Wenwu Li^{2

5}, Jun Li⁶, Jianhua Zhang⁶, Kenji Watanabe⁷, Takashi Taniguchi⁸, Keiji Ueno⁹, Kazuhito Tsukagoshi¹⁰, Ching-Hwa Ho¹¹, Junhao Chu^{2

5}, Po-Wen Chiu⁴, Mengjiao Li⁶, Wen-Wei Wu¹, Yen-Fu Lin^{3

12}

Affiliations

¹ Department of Materials Science and Engineering, National Yang Ming Chiao Tung University, Hsinchu 30010, Taiwan.
² Shanghai Frontiers Science Research Base of Intelligent Optoelectronics and Perception, Institute of Optoelectronics, Fudan University, Shanghai 200433, China.
³ Department of Physics, National Chung Hsing University, Taichung 40227, Taiwan.
⁴ Institute of Electronics Engineering, National Tsing Hua University, Hsinchu 30013, Taiwan.
⁵ State Key Laboratory of Photovoltaic Science and Technology, Department of Materials Science, Fudan University, Shanghai 200433, China.
⁶ School of Microelectronics, Shanghai University, Jiading, Shanghai 201800, China.
⁷ Research Center for Electronic and Optical Materials, National Institute for Materials Science, 1-1 Namiki, Tsukuba 305-0044, Japan.
⁸ Research Center for Materials Nanoarchitectonics, National Institute for Materials Science, 1-1 Namiki, Tsukuba 305-0044, Japan.
⁹ Department of Chemistry, Graduate School of Science and Engineering, Saitama University, Saitama 338-8570, Japan.
¹⁰ International Center for Materials Nanoarchitectonics, National Institute for Materials Science, Tsukuba 305-0044, Japan.
¹¹ Graduate Institute of Applied Science and Technology, National Taiwan University of Science and Technology, Taipei 106, Taiwan.
¹² Department of Material Science and Engineering, Institutes of Nanoscience, i-Center for Advanced Science and Technology (i-CAST), National Chung Hsing University, Taichung 40227, Taiwan.

Abstract

Silicon CMOS-based computing-in-memory encounters design and power challenges, especially in logic-in-memory scenarios requiring nonvolatility and reconfigurability. Here, we report a universal design for nonvolatile reconfigurable devices featuring a 2D/3D heterointegrated configuration. By leveraging the photo-controlled charge trapping/detrapping process and the partially top-gated energy band landscape, the van der Waals heterostacking achieves polarity storage and logic reconfigurable characteristics, respectively. Precise polarity tunability, logic nonvolatility, robustness against high temperature (at 85°C), and near-ideal subthreshold swing (80 mV dec^-1) can be done. A comprehensive investigation of dynamic charge fluctuations provides a holistic understanding of the origins of nonvolatile reconfigurability (a trap level of 10¹³ cm^-2 eV^-1). Furthermore, we cascade such nonvolatile reconfigurable units into a monolithic circuit layer to demonstrate logic-in-memory computing possibilities, such as high-gain (65 at V_dd = 0.5 V) logic gates. This work provides an innovative 3D heterointegration prototype for future computing-in-memory hardware.