Design of Power Amplifiers for BDS-3 Terminal Based on InGaP/GaAs HBT MMIC and LGA Technology

Zhenbing Li; Junjie Huang; Jinrong Zhang; Shilin Jia; Haoyang Sun; Gang Li; Guangjun Wen

doi:10.3390/mi14111995

Design of Power Amplifiers for BDS-3 Terminal Based on InGaP/GaAs HBT MMIC and LGA Technology

Micromachines (Basel). 2023 Oct 27;14(11):1995. doi: 10.3390/mi14111995.

Authors

Zhenbing Li¹, Junjie Huang¹, Jinrong Zhang¹, Shilin Jia¹, Haoyang Sun¹, Gang Li², Guangjun Wen¹

Affiliations

¹ School of Information and Communication Engineering, University of Electronic Science and Technology of China, Chengdu 611731, China.
² School of Information and Software Engineering, University of Electronic Science and Technology of China, Chengdu 610054, China.

Abstract

With the development and popularization of the Beidou-3 navigation satellite system (BDS-3), to ensure its unique short message function, it is necessary to integrate a radio frequency (RF) transmitting circuit with high performance in the BDS-3 terminal. As the key device in an RF transmitting circuit, the RF power amplifier (PA) largely determines the comprehensive performance of the circuit with its transmission power, efficiency, linearity, and integration. Therefore, in this paper, an L-band highly integrated PA chip compatible with 3 W and 5 W output power is designed in InGaP/GaAs heterojunction bipolar transistor (HBT) technology combined with temperature-insensitive adaptive bias technology, class-F harmonic suppression technology, analog pre-distortion technology, temperature-insensitive adaptive power detection technology, and land grid array (LGA) packaging technology. Additionally, three auxiliary platforms are proposed, dedicated to the simulation and optimization of the same type of PA designs. The simulation results show that at the supply voltage of 5 V and 3.5 V, the linear gain of the PA chip reaches 39.4 dB and 38.7 dB, respectively; the output power at 1 dB compression point (P1dB) reaches 37.5 dBm and 35.1 dBm, respectively; the saturated output power (Psat) reaches 38.2 dBm and 36.2 dBm, respectively; the power added efficiency (PAE) reaches 51.7% and 48.2%, respectively; and the higher harmonic suppression ratios are less than -62 dBc and -65 dBc, respectively. The size of the PA chip is only 6 × 4 × 1 mm³. The results also show that the PA chip has high gain, high efficiency, and high linearity under both output power conditions, which has obvious advantages over similar PA chip designs and can meet the short message function of the BDS-3 terminal in various application scenarios.

Keywords: BDS-3 terminal; analog pre-distortion; class-F power amplifier; compatible power amplifier chips; short message function; temperature-insensitive adaptive bias.

Grants and funding

This work was supported in part by the Guangdong Provincial Research and Development Plan in Key Areas (project contract No. 2019B010141001), in part by the National Key R&D Program (project contract No. 2018YFB1802102 and 2018AAA010-3203), in part by the Sichuan Provincial Science and Technology Planning Program (project contracts No. 2021YFG0013, 2021YFH0133, 2022YFG0230, and 2023YFG0040), in part by the 131 Project (Z2F2), in part by the Joint Project of China Mobile Research Institute & X-NET (2022H002), and in part by the Fund Project of Intelligent Terminal Key Laboratory of Sichuan Province (SCITLAB-1015). And the APC was funded by the Guangdong Provincial Research and Development Plan in Key Areas (project contract No. 2019B010141001).