Integrated Logic Circuits Based on Wafer-Scale 2D-MoS2 FETs Using Buried-Gate Structures

Ju-Ah Lee; Jongwon Yoon; Seungkwon Hwang; Hyunsang Hwang; Jung-Dae Kwon; Seung-Ki Lee; Yonghun Kim

doi:10.3390/nano13212870

Integrated Logic Circuits Based on Wafer-Scale 2D-MoS₂ FETs Using Buried-Gate Structures

Nanomaterials (Basel). 2023 Oct 30;13(21):2870. doi: 10.3390/nano13212870.

Authors

Ju-Ah Lee^{1

2}, Jongwon Yoon¹, Seungkwon Hwang¹, Hyunsang Hwang³, Jung-Dae Kwon¹, Seung-Ki Lee², Yonghun Kim¹

Affiliations

¹ Department of Energy and Electronic Materials, Surface Materials Division, Korea Institute of Materials Science (KIMS), Changwon 51508, Republic of Korea.
² School of Materials Science and Engineering, Pusan National University, Busan 46241, Republic of Korea.
³ Center for Single Atom-Based Semiconductor Device, Department of Materials Science and Engineering, Pohang University of Science and Technology (POSTECH), Pohang 37673, Republic of Korea.

Abstract

Two-dimensional (2D) transition-metal dichalcogenides (TMDs) materials, such as molybdenum disulfide (MoS₂), stand out due to their atomically thin layered structure and exceptional electrical properties. Consequently, they could potentially become one of the main materials for future integrated high-performance logic circuits. However, the local back-gate-based MoS₂ transistors on a silicon substrate can lead to the degradation of electrical characteristics. This degradation is caused by the abnormal effect of gate sidewalls, leading to non-uniform field controllability. Therefore, the buried-gate-based MoS₂ transistors where the gate electrodes are embedded into the silicon substrate are fabricated. The several device parameters such as field-effect mobility, on/off current ratio, and breakdown voltage of gate dielectric are dramatically enhanced by field-effect mobility (from 0.166 to 1.08 cm²/V·s), on/off current ratio (from 4.90 × 10⁵ to 1.52 × 10⁷), and breakdown voltage (from 15.73 to 27.48 V) compared with a local back-gate-based MoS₂ transistor, respectively. Integrated logic circuits, including inverters, NAND, NOR, AND, and OR gates, were successfully fabricated by 2-inch wafer-scale through the integration of a buried-gate MoS₂ transistor array.

Keywords: buried-gate structure; gate controllability; logic circuits; molybdenum disulfide; wafer-scale integration.

Grants and funding

This study was supported by the Fundamental Research Program (PNK9020) of the Korean Institute of Materials Science (KIMS) and the Energy Technology Development Program of the Korean Institute of Energy Technology Evaluation and Planning (KETEP) (Grant No. RS-2023-00301944), and Technology Innovation Program (20018106, Development of 8 in. atomic layer deposition system for 2D materials and applications as photosensors and 20022508, Development of ultrahigh temperature activator and core process technology for SiC devices) of the Ministry of Trade, Industry and Energy (MOTIE, Korea). Also, this study was supported by the National Research Council of Science and Technology (NST) grant by the Korean Government (MSIT) (No. CPS22191-100).