CMOS backend-of-line compatible memory array and logic circuitries enabled by high performance atomic layer deposited ZnO thin-film transistor

Wenhui Wang; Ke Li; Jun Lan; Mei Shen; Zhongrui Wang; Xuewei Feng; Hongyu Yu; Kai Chen; Jiamin Li; Feichi Zhou; Longyang Lin; Panpan Zhang; Yida Li

doi:10.1038/s41467-023-41868-5

CMOS backend-of-line compatible memory array and logic circuitries enabled by high performance atomic layer deposited ZnO thin-film transistor

Nat Commun. 2023 Sep 28;14(1):6079. doi: 10.1038/s41467-023-41868-5.

Authors

Wenhui Wang^#¹, Ke Li^#¹, Jun Lan¹, Mei Shen¹, Zhongrui Wang², Xuewei Feng³, Hongyu Yu¹, Kai Chen¹, Jiamin Li¹, Feichi Zhou¹, Longyang Lin⁴, Panpan Zhang⁵, Yida Li⁶

Affiliations

¹ School of Microelectronics, Southern University of Science and Technology, 518055, Shenzhen, China.
² Department of Electrical and Electronic Engineering, The University of Hong Kong, 999077, Hong Kong SAR, China.
³ Shanghai Jiao Tong University, 200240, Shanghai, China.
⁴ School of Microelectronics, Southern University of Science and Technology, 518055, Shenzhen, China. linly@sustech.edu.cn.
⁵ State Key Laboratory of Information Photonics and Optical Communications, Beijing University of Posts and Telecommunications, 100876, Beijing, China. tanji_ic@bupt.edu.cn.
⁶ School of Microelectronics, Southern University of Science and Technology, 518055, Shenzhen, China. liyd3@sustech.edu.cn.

^# Contributed equally.

Abstract

The development of high-performance oxide-based transistors is critical to enable very large-scale integration (VLSI) of monolithic 3-D integrated circuit (IC) in complementary metal oxide semiconductor (CMOS) backend-of-line (BEOL). Atomic layer deposition (ALD) deposited ZnO is an attractive candidate due to its excellent electrical properties, low processing temperature below copper interconnect thermal budget, and conformal sidewall deposition for novel 3D architecture. An optimized ALD deposited ZnO thin-film transistor achieving a record field-effect and intrinsic mobility (µ_FE /µ_o) of 85/140 cm²/V·s is presented here. The ZnO TFT was integrated with HfO₂ RRAM in a 1 kbit (32 × 32) 1T1R array, demonstrating functionalities in RRAM switching. In order to co-design for future technology requiring high performance BEOL circuitries implementation, a spice-compatible model of the ZnO TFTs was developed. We then present designs of various ZnO TFT-based inverters, and 5-stage ring oscillators through simulations and experiments with working frequency exceeding 10's of MHz.

Abstract

Grants and funding