Novel hardware architectures for dynamic reconfigurable implementation of 64-bit MISTY1 and KASUMI block ciphers are proposed to enhance the performance of cryptographic chips for secure IoT applications. The SRL32 primitive (Reconfigurable Look up Tables-RLUTs) and DPR (Dynamic Partial Reconfiguration) are employed to reconfigure single round MISTY1 / KASUMI algorithms on the run-time. The RLUT based architecture attains dynamic logic functionality without extra hardware resources by internally modifying the LUT contents. The proposed adaptive reconfiguration can be adopted as a productive countermeasure against malicious attacks with the added advantage of less reconfiguration time (RT). On the other hand, the block architecture reconfigures the core hardware by externally uploading the partial bit stream and has significant advantages in terms of low area implementation and power reduction. Implementation was carried out on FPGA, Xilinx Virtex 7. The results showed remarkable results with very low area of 668 / 514 CLB slices consuming 460 / 354 mW for RLUT and DPR architectures respectively. Moreover, the throughput obtained for RLUT architecture was found as 364 Mbps with very less RT of 445 nsec while DPR architecture achieved speed of 176 Mbps with RT of 1.1 msec. The novel architectures outperform the stand-alone existing hardware designs of MISTY1 and KASUMI implementations by adding the dynamic reconfigurability while at the same achieving high performance in terms of area and throughput. Design details of proposed unified architectures and comprehensive analysis is described.
Copyright: © 2023 Jiexian et al. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.