Sub-5 nm Gate-Length Monolayer Selenene Transistors

Qiang Li; Xingyi Tan; Yongming Yang; Xiaoyong Xiong; Teng Zhang; Zhulin Weng

doi:10.3390/molecules28145390

Sub-5 nm Gate-Length Monolayer Selenene Transistors

Molecules. 2023 Jul 13;28(14):5390. doi: 10.3390/molecules28145390.

Authors

Qiang Li¹, Xingyi Tan², Yongming Yang¹, Xiaoyong Xiong¹, Teng Zhang¹, Zhulin Weng¹

Affiliations

¹ College of Intelligent Systems Science and Engineering, Hubei Minzu University, Enshi 445000, China.
² Department of Physics, Chongqing Three Gorges University, Chongqing 404100, China.

Abstract

Two-dimensional (2D) semiconductors are being considered as alternative channel materials as silicon-based field-effect transistors (FETs) have reached their scaling limits. Recently, air-stable 2D selenium nanosheet FETs with a gate length of 5 µm were experimentally produced. In this study, we used an ab initio quantum transport approach to simulate sub-5 nm gate-length double-gate monolayer (ML) selenene FETs. When considering negative-capacitance technology and underlap, we found that 3 nm gate-length p-type ML selenene FETs can meet the 2013 ITRS standards for high-performance applications along the armchair and zigzag directions in the 2028 horizon. Therefore, ML selenene has the potential to be a channel material that can scale Moore's law down to a gate length of 3 nm.

Keywords: density functional theory; monolayer selenene; quantum transport simulation; sub-5 nm gate length.

Abstract

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