Integrated circuits (ICs) are challenged to deliver historically anticipated performance improvements while increasing the cost and complexity of the technology with each generation. Front-end-of-line (FEOL) processes have provided various solutions to this predicament, whereas the back-end-of-line (BEOL) processes have taken a step back. With continuous IC scaling, the speed of the entire chip has reached a point where its performance is determined by the performance of the interconnect that bridges billions of transistors and other devices. Consequently, the demand for advanced interconnect metallization rises again, and various aspects must be considered. This review explores the quest for new materials for successfully routing nanoscale interconnects. The challenges in the interconnect structures as physical dimensions shrink are first explored. Then, various problem-solving options are considered based on the properties of materials. New materials are also introduced for barriers, such as 2D materials, self-assembled molecular layers, high-entropy alloys, and conductors, such as Co and Ru, intermetallic compounds, and MAX phases. The comprehensive discussion of each material includes state-of-the-art studies ranging from the characteristics of materials by theoretical calculation to process applications to the current interconnect structures. This review intends to provide a materials-based implementation strategy to bridge the gap between academia and industry.
Keywords: electrical resistivity; electromigration; integrated circuit; interconnect; metallization; semiconductor; size effect.
© 2023 The Authors. Advanced Science published by Wiley-VCH GmbH.