Low-phase noise and wideband phased-locked loops (PLLs) are crucial for high-data rate communication and imaging systems. Sub-millimeter-wave (sub-mm-wave) PLLs typically exhibit poor performance in terms of noise and bandwidth due to higher device parasitic capacitances, among other reasons. In this regard, a low-phase-noise, wideband, integer-N, type-II phase-locked loop was implemented in the 22 nm FD-SOI CMOS process. The proposed wideband linear differential tuning I/Q voltage-controlled oscillator (VCO) achieves an overall frequency range of 157.5-167.5 GHz with 8 GHz linear tuning and a phase noise of -113 dBc/Hz @ 100 KHz. Moreover, the fabricated PLL produces a phase noise less than -103 dBc/Hz @ 1 KHz and -128 dBc/Hz @ 100 KHz, corresponding to the lowest phase noise generated by a sub-millimeter-wave PLL to date. The measured RF output saturated power and DC power consumption of the PLL are 2 dBm and 120.75 mW, respectively, whereas the fabricated chip comprising a power amplifier and an integrated antenna occupies an area of 1.25 × 0.9 mm2.
Keywords: frequency divider; phase noise; phase-locked loop; sub-millimeter-wave; voltage-controlled oscillator.