Rational design of formamidine tin-based perovskite solar cell with 30% potential efficiency via 1-D device simulation

Kaiwen Liang; Like Huang; Tianzhou Wang; Chaofeng Wang; Yi Guo; Yunliang Yue; Xiaohui Liu; Jing Zhang; Ziyang Hu; Yuejin Zhu

doi:10.1039/d2cp05226a

Rational design of formamidine tin-based perovskite solar cell with 30% potential efficiency via 1-D device simulation

Phys Chem Chem Phys. 2023 Mar 29;25(13):9413-9427. doi: 10.1039/d2cp05226a.

Authors

Kaiwen Liang¹, Like Huang^{1

2}, Tianzhou Wang¹, Chaofeng Wang¹, Yi Guo¹, Yunliang Yue³, Xiaohui Liu¹, Jing Zhang¹, Ziyang Hu¹, Yuejin Zhu¹

Affiliations

¹ Department of Microelectronic Science and Engineering School of Physical Science and Technology, Ningbo University, Fenghua Road 818, Ningbo 315211, China. huanglike@nbu.edu.cn.
² National Laboratory of Solid State Microstructures, Nanjing University, Nanjing 210093, China.
³ School of Information Engineering, Yangzhou University, Yangzhou 225127, China.

PMID: 36928894
DOI: 10.1039/d2cp05226a

Abstract

As a promising photovoltaic technology, halide perovskite solar cells (PSCs) have recently attracted wide attention. This work presents a systematic simulation of low bandgap formamidinium tin iodide (FASnI₃)-based p-n heterojunction PSCs to investigate the effects of multiple optoelectronic variations on the photovoltaic performance. The structures of the simulated devices are n-i-p, electron transport layer-free (ETL-free), hole transport layer-free (HTL-free), and inverted HTL-free. The simulation is conducted with the Solar Cell Capacitance Simulator (SCAPS-1D). The power conversion efficiencies (PCEs) dramatically decrease when the acceptor doping density (N_A) of the absorber layer exceeds 10¹⁶ cm^-3. For all devices, the photovoltaic parameters dramatically decrease when the absorber defect density (N_t) is over 10¹⁵ cm^-3, and the best absorber layer thickness is 1000 nm. It should be pointed out that the N_t and the interface defect layer (IDL) are the primary culprits that seriously affect the device performance. When the interfacial defect density (N_it) exceeds 10¹² cm^-3, PCEs begin to decline significantly. Therefore, paying attention to these defect layers is necessary to improve the PCE. Furthermore, the proper conduction band offset (CBO) between the electron transport layer (ETL) and absorber layer positively affects PSCs' performance. These simulation results help fabricate highly efficient and environment-friendly narrow bandgap PSCs.