Controlling Drain Side Tunneling Barrier Width in Electrically Doped PNPN Tunnel FET

Micromachines (Basel). 2023 Jan 24;14(2):301. doi: 10.3390/mi14020301.

Abstract

In this paper, we propose and investigate an electrically doped (ED) PNPN tunnel field effect transistor (FET), in which the drain side tunneling barrier width is effectively controlled to obtain a suppressed ambipolar current. We present that the proposed PNPN tunnel FETs can be realized without chemically doped junctions by applying the polarity bias concept to a doped N+/P- starting structure. Using numerical device simulations, we demonstrate how the tunneling barrier width on the drain side can be influenced by several design parameters, such as the gap length between the channel and the drain (Lgap), the working function of the polarity gate, and the dielectric material of the spacer. The simulation results show that an ED PNPN tunneling FET with an ED drain, which has been explored for the first time, exhibits a low ambipolar current of 5.87 × 10-16 A/µm at a gap length of 20 nm. The ambipolar current is reduced by six orders of magnitude compared to that which occurs with a conventional ED PNPN tunnel FET with a uniformly doped drain, while the average subthreshold slope and the ON state and OFF state currents remained nearly identical.

Keywords: PNPN tunnel FET; TCAD simulation; ambipolar current; electrically doping; tunneling barrier width.

Grants and funding

This research was funded in part by the Jimei University Doctoral Research Startup Fund, grant number ZQ2018015, and in part by the Fujian Province Young and Middle-aged Teacher Education Research Project, grant number JAT210979, and in part by the Natural Science Foundation of Fujian Province, grant number 2020J05150.