A 40 MHz 11-Bit ENOB Delta Sigma ADC for Communication and Acquisition Systems

Hussein Fakhoury; Chadi Jabbour; Van-Tam Nguyen

doi:10.3390/s23010036

A 40 MHz 11-Bit ENOB Delta Sigma ADC for Communication and Acquisition Systems

Sensors (Basel). 2022 Dec 20;23(1):36. doi: 10.3390/s23010036.

Authors

Hussein Fakhoury¹, Chadi Jabbour², Van-Tam Nguyen²

Affiliations

¹ Scalinx, 75013 Paris, France.
² Telecom Paris, 91120 Palaiseau, France.

Abstract

This paper describes a Delta Sigma ADC IC that embeds a 5th-order Continuous-Time Delta Sigma modulator with 40 MHz signal bandwidth, a low ripple 20 to 80 MS/s variable-rate digital decimation filter, a bandgap voltage reference, and high-speed CML buffers on a single die. The ADC also integrates on-chip calibrations for RC time-constant variation and quantizer offset. The chip was fabricated in a 1P7M 65 nm CMOS process. Clocked at 640 MHz, the Continuous-Time Delta Sigma modulator achieves 11-bit ENOB and 76.5 dBc THD up to 40 MHz of signal bandwidth while consuming 82.3 mW.

Keywords: CMOS design; Delta Sigma modulators; analog to digital conversion; decimation filter.

MeSH terms

CLOCK Proteins*
Communication*

Substances

CLOCK Proteins

Grants and funding

This research received funding from European project CORTIF CA116.