Skyrmion based 3D low complex runtime reconfigurable architecture design methodology of universal logic gate

Santhosh Sivasubramani; Bibekananda Paikaray; Mahathi Kuchibhotla; Arabinda Haldar; Chandrasekhar Murapaka; Amit Acharyya

doi:10.1088/1361-6528/acaf32

Skyrmion based 3D low complex runtime reconfigurable architecture design methodology of universal logic gate

Nanotechnology. 2023 Jan 20;34(13). doi: 10.1088/1361-6528/acaf32.

Authors

Santhosh Sivasubramani¹, Bibekananda Paikaray², Mahathi Kuchibhotla³, Arabinda Haldar³, Chandrasekhar Murapaka², Amit Acharyya¹

Affiliations

¹ Advanced Embedded Systems and IC Design Laboratory, Department of Electrical Engineering, Indian Institute of Technology (IIT) Hyderabad, 502284, India.
² Department of Materials Science and Metallurgical Engineering, Indian Institute of Technology (IIT) Hyderabad, 502284, India.
³ Department of Physics, Indian Institute of Technology (IIT) Hyderabad, 502284, India.

PMID: 36584387
DOI: 10.1088/1361-6528/acaf32

Abstract

In this study, we introduce the area efficient low complex runtime reconfigurable architecture design methodology based on Skyrmion logic for universal logic gate (ULG) i.e. NOR/NAND implementation using micromagnetic simulations. We have modelled the two input 3D device structure using bilayer ferromagnet/heavy metal where the magnetic tunnel junctions inject and detect the input and output skyrmions by exploiting the input reversal mechanism. The implementation of NOR and NAND is performed using this same device where it is reconfigured runtime with enhanced tunability by the ON and OFF state of current passing through a non magnetic metallic gate respectively. This gate acts as a barrier for skyrmion motion (additional control mechanism) to realize the required Skyrmion logic output states. To the best of authors's knowledge the boolean optimizations and the mapping logic have been presented for the first time to demonstrate the functionalities of the NOR/NAND implementation. This proposed architecture design methodology of ULG leads to reduced device footprint with regard to the number of thin film structures proposed, low complexity in terms of fabrication and also providing runtime reconfigurability to reduce the number of physical designs to achieve all truth table entries (∼75% device footprint reduction). The proposed 3D ULG architecture design benefits from the miniaturization resulting in opening up a new perspective for magneto-logic devices.

Keywords: 3D low complex design; area efficient design; boolean optimization; nano architecture; runtime reconfigurability; skyrmion logic.