Second-order associative memory circuit hardware implemented by the evolution from battery-like capacitance to resistive switching memory

Guangdong Zhou; Xiaoye Ji; Jie Li; Feichi Zhou; Zhekang Dong; Bingtao Yan; Bai Sun; Wenhua Wang; Xiaofang Hu; Qunliang Song; Lidan Wang; Shukai Duan

doi:10.1016/j.isci.2022.105240

Second-order associative memory circuit hardware implemented by the evolution from battery-like capacitance to resistive switching memory

iScience. 2022 Sep 28;25(10):105240. doi: 10.1016/j.isci.2022.105240. eCollection 2022 Oct 21.

Authors

Guangdong Zhou¹, Xiaoye Ji², Jie Li³, Feichi Zhou³, Zhekang Dong², Bingtao Yan¹, Bai Sun⁴, Wenhua Wang¹, Xiaofang Hu¹, Qunliang Song¹, Lidan Wang¹, Shukai Duan¹

Affiliations

¹ College of Artificial Intelligence, School of Materials and Energy, Southwest University, Chongqing 400715, PR China.
² College of Electrical Engineering, Zhejiang University, Hangzhou 310027, PR China.
³ Shenzhen-Hong Kong College of Microelectronics, Southern University of Science and Technology, Shenzhen 518055, China.
⁴ Department of Mechanics and Mechatronics Engineering, Centre for Advanced Materials Joining, Waterloo Institute for Nanotechnology, University of Waterloo, Waterloo, ON N2L 3G1, Canada.

Abstract

Memristor-based Pavlov associative memory circuit presented today only realizes the simple condition reflex process. The secondary condition reflex endows the simple condition reflex process with more bionic, but it is only demonstrated in design and involves the large number of redundant circuits. A FeO _x -based memristor exhibits an evolution process from battery-like capacitance (BLC) state to resistive switching (RS) memory as the I-V sweeping increase. The BLC is triggered by the active metal ion and hydroxide ion originated from water molecule splitting at different interfaces, while the RS memory behavior is dominated by the diffusion and migration of ion in the FeO _x switching function layer. The evolution processes share the nearly same biophysical mechanism with the second-order conditioning. It enables a hardware-implemented second-order associative memory circuit to be feasible and simple. This work provides a novel path to realize the associative memory circuit with the second-order conditioning at hardware level.

Keywords: Hardware architecture; Memory structure.