The inner spacer thickness (TIS) variations in sub-3-nm, node 3-stacked, nanosheet field-effect transistors (NSFETs) were investigated using computer-aided design simulation technology. Inner spacer formation requires a high selectivity of SiGe to Si, which causes inevitable TIS variation (ΔTIS). The gate length (LG) depends on the TIS. Thus, the DC/AC performance is significantly affected by ΔTIS. Because the effects of ΔTIS on the performance depend on which inner spacer is varied, the sensitivities of the performance to the top, middle, and bottom (T, M, and B, respectively) ΔTIS should be studied separately. In addition, the source/drain (S/D) recess process variation that forms the parasitic bottom transistor (trpbt) should be considered with ΔTIS because the gate controllability over trpbt is significantly dependent on ΔTIS,B. If the S/D recess depth (TSD) variation cannot be completely eliminated, reducing ΔTIS,B is crucial for suppressing the effects of trpbt. It is noteworthy that reducing ΔTIS,B is the most important factor when the TSD variation occurs, whereas reducing ΔTIS,T and ΔTIS,M is crucial in the absence of TSD variation to minimize the DC performance variation. As the TIS increases, the gate capacitance (Cgg) decreases owing to the reduction in both parasitic and intrinsic capacitance, but the sensitivity of Cgg to each ΔTIS is almost the same. Therefore, the difference in performance sensitivity related to AC response is also strongly affected by the DC characteristics. In particular, since TSD of 5 nm increases the off-state current (Ioff) sensitivity to ΔTIS,B by a factor of 22.5 in NFETs, the ΔTIS,B below 1 nm is essential for further scaling and yield enhancement.
Keywords: TCAD simulation; inner spacer; inner spacer thickness variation; nanosheet FET; performance sensitivity; source/drain recess depth.