Fabricating ultrathin silicon (Si) channels down to critical dimension (CD) <10 nm, a key capability to implementing cutting-edge microelectronics and quantum charge-qubits, has never been accomplished via an extremely low-cost catalytic growth. In this work, 3D stacked ultrathin Si nanowires (SiNWs) are demonstrated, with width and height of Wnw = 9.9 ± 1.2 nm (down to 8 nm) and Hnw = 18.8 ± 1.8 nm, that can be reliably grown into the ultrafine sidewall grooves, approaching to the CD of 10 nm technology node, thanks to a new self-delimited droplet control strategy. Interestingly, the cross-sections of the as-grown SiNW channels can also be easily tailored from fin-like to sheet-like geometries by tuning the groove profile, while a sharply folding guided growth indicates a unique capability to produce closely-packed multiple rows of stacked SiNWs, out of a single run growth, with the minimal use of catalyst metal. Prototype field effect transistors are also successfully fabricated, achieving Ion/off ratio and sub-threshold swing of >106 and 125 mV dec-1 , respectively. These results highlight the unexplored potential of versatile catalytic growth to compete with, or complement, the advanced top-down etching technology in the exploitation of monolithic 3D integration of logic-in-memory, neuromorphic and charge-qubit applications.
Keywords: 3D integration; catalytic growth; in-plane solid-liquid-solid; ultrathin Si nanowires.
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