Large aperture ultrasonic arrays can be implemented by tiling together multiple pretested modules of high-density acoustic arrays with closely integrated multiplexing and buffering electronics to form a larger aperture with high yield. These modular arrays can be used to implement large 1.75D array apertures capable of focusing in elevation for uniform slice thickness along the axial direction which can improve image contrast. An important goal for large array tiling is obtaining high yield and sensitivity while reducing extraneous image artifacts. We have been developing tileable acoustic-electric modules for the implementation of large array apertures utilizing Application Specific Integrated Circuits (ASICs) implemented using 0.35 μ m high voltage (50 V) CMOS. Multiple generations of ASICs have been designed and tested. The ASICs were integrated with high-density transducer arrays for acoustic testing and imaging. The modules were further interfaced to a Verasonics Vantage imaging system and were used to image industry standard ultrasound phantoms. The first-generation modules comprise ASICs with both multiplexing and buffering electronics on-chip and have demonstrated a switching artifact which was visible in the images. A second-generation ASIC design incorporates low switching injection circuits which effectively mitigate the artifacts observed with the first-generation devices. Here, we present the architecture of the two ASIC designs and module types as well imaging results that demonstrate reduction in switching artifacts for the second-generation devices.