Impact of Stacking-Up and Scaling-Down Bit Cells in 3D NAND on Their Threshold Voltages

Dongwoo Lee; Changhwan Shin

doi:10.3390/mi13071139

Impact of Stacking-Up and Scaling-Down Bit Cells in 3D NAND on Their Threshold Voltages

Micromachines (Basel). 2022 Jul 18;13(7):1139. doi: 10.3390/mi13071139.

Authors

Dongwoo Lee¹, Changhwan Shin²

Affiliations

¹ Department of Semiconductor and Display Engineering, Sungkyunkwan University, Suwon 16419, Korea.
² School of Electrical Engineering, Korea University, Seoul 02841, Korea.

Abstract

Over the past few decades, NAND flash memory has advanced with exponentially-increasing bit growth. As bit cells in 3D NAND flash memory are stacked up and scaled down together, some potential challenges should be investigated. In order to reasonably predict those challenges, a TCAD (technology computer-aided design) simulation for 3D NAND structure in mass production has been run. By aggressively stacking-up and scaling-down bit cells in a string, the structure of channel hole was varied from a macaroni to nanowire. This causes the threshold voltage difference (ΔV_th) between the top cell and bottom cell in the same string. In detail, ΔV_th between the top cell and bottom cell mostly depends on the xy-scaling, but the way how ΔV_th is affected is not very dependent on the stack height.

Keywords: 3D NAND flash; macaroni channel; nanowire channel; tapered channel.

Abstract

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