An accurate epileptic seizure detector using intracranial electroencephalography (iEEG) recordings, suitable for low-power wearable/implantable applications, is presented. Eleven time-domain features with low hardware complexity are employed in the feature pool of the seizure detector. A novel two-step feature ranking algorithm based on maximum discrimination minimum redundancy (MDMR) is proposed to identify the most discriminating features in a patient-specific manner during a training phase. Subsequently, the top-ranked features are extracted in a two-stage energy-efficient architecture in which the second stage is activated by a controller to avoid unnecessary energy consumption imposed by multiple feature extraction during the long period of non-seizure states. The effective number of features which are continuously extracted is reduced in this work. Moreover, a patient-specific data reduction technique which selects the most informative and discriminating iEEG channels is also proposed. The presented channel selection technique reaches 68% data reduction on average for the tested patients and reduces the computational complexity. The proposed algorithm is implemented on Cyclone V FPGA of Terasic DE10-standard board. It is tested on twelve patients with short-term and long-term seizures from the Bern Inselspital dataset. The FPGA implementation results reveal an excellent sensitivity of 100% for all patients and remarkable specificity and detection delay improvement compared to the state-of-the-art. The average dynamic power consumption is 0.49 mW which is in the acceptable range for low-power wearable/implantable applications. In addition, a new figure-of-merit (FoM_SD) is defined to consider the major parameters of the seizure detectors. The outstanding FoM_SD of this work is 0.464 which outperforms the state-of-the-art.