A vertical WSe2-MoSe2 p-n heterostructure with tunable gate rectification

Hailing Liu; Sajjad Hussain; Asif Ali; Bilal Abbas Naqvi; Dhanasekaran Vikraman; Woonyoung Jeong; Wooseok Song; Ki-Seok An; Jongwan Jung

doi:10.1039/c8ra03398f

A vertical WSe₂-MoSe₂ p-n heterostructure with tunable gate rectification

RSC Adv. 2018 Jul 17;8(45):25514-25518. doi: 10.1039/c8ra03398f. eCollection 2018 Jul 16.

Authors

Hailing Liu^{1

2}, Sajjad Hussain^{1

2}, Asif Ali^{1

2}, Bilal Abbas Naqvi^{1

2}, Dhanasekaran Vikraman³, Woonyoung Jeong^{1

2}, Wooseok Song⁴, Ki-Seok An⁴, Jongwan Jung^{1

2}

Affiliations

¹ Graphene Research Institute, Sejong University Seoul 143-747 Republic of Korea jwjung@sejong.ac.kr.
² Institute of Nano and Advanced Materials Engineering, Sejong University Seoul 143-747 Republic of Korea.
³ Division of Electronics and Electrical Engineering, Dongguk University-Seoul Seoul 04620 Republic of Korea.
⁴ Thin Film Materials Research Center, Korea Research Institute of Chemical Technology Daejon 305-600 Korea.

Abstract

Here, we report the synthesis of a vertical MoSe₂/WSe₂ p-n heterostructure using a sputtering-CVD method. Unlike the conventional CVD method, this method produced a continuous MoSe₂/WSe₂ p-n heterostructure. WSe₂ and MoSe₂ back-gated field effect transistors (FETs) exhibited good gate modulation behavior, and high hole and electron mobilities of ∼2.2 and ∼15.1 cm² V^-1 s^-1, respectively. The fabricated vertical MoSe₂/WSe₂ p-n diode showed rectifying I-V behavior with back-gate tunability. The rectification ratio of the diode was increased with increasing gate voltage, and was increased from ∼18 to ∼1600 as the gate bias increased from -40 V to +40 V. This is attributed to the fact that the barrier height between p-WSe₂ and n-MoSe₂ is modulated due to the back-gate bias. The rectification ratio is higher than the previously reported values for the TMDC p-n heterostructure grown by CVD.