Author Correction: A graph placement methodology for fast chip design
Nature
.
2022 Apr;604(7906):E24.
doi: 10.1038/s41586-022-04657-6.
Authors
Azalia Mirhoseini
#
1
,
Anna Goldie
#
2
3
,
Mustafa Yazgan
4
,
Joe Wenjie Jiang
5
,
Ebrahim Songhori
5
,
Shen Wang
5
,
Young-Joon Lee
4
,
Eric Johnson
5
,
Omkar Pathak
4
,
Azade Nazi
5
,
Jiwoo Pak
4
,
Andy Tong
4
,
Kavya Srinivasa
4
,
William Hang
6
,
Emre Tuncer
4
,
Quoc V Le
5
,
James Laudon
5
,
Richard Ho
4
,
Roger Carpenter
4
,
Jeff Dean
5
Affiliations
1
Google Research, Brain Team, Google, Mountain View, CA, USA. azalia@google.com.
2
Google Research, Brain Team, Google, Mountain View, CA, USA. agoldie@google.com.
3
Computer Science Department, Stanford University, Stanford, CA, USA. agoldie@google.com.
4
Google Chip Implementation and Infrastructure (CI2) Team, Google, Sunnyvale, CA, USA.
5
Google Research, Brain Team, Google, Mountain View, CA, USA.
6
Computer Science Department, Stanford University, Stanford, CA, USA.
#
Contributed equally.
PMID:
35361999
DOI:
10.1038/s41586-022-04657-6
No abstract available
Publication types
Published Erratum