Dielectric Walls/Layers Modulated 3D Periodically Structured SERS Chips: Design, Batch Fabrication, and Applications

Yi Tian; Haifeng Hu; Peipei Chen; Fengliang Dong; Hui Huang; Lihua Xu; Lanqin Yan; Zhiwei Song; Taoran Xu; Weiguo Chu

doi:10.1002/advs.202200647

Dielectric Walls/Layers Modulated 3D Periodically Structured SERS Chips: Design, Batch Fabrication, and Applications

Adv Sci (Weinh). 2022 May;9(15):e2200647. doi: 10.1002/advs.202200647. Epub 2022 Mar 24.

Authors

Yi Tian¹, Haifeng Hu¹, Peipei Chen^{1

2}, Fengliang Dong^{1

2}, Hui Huang¹, Lihua Xu¹, Lanqin Yan¹, Zhiwei Song¹, Taoran Xu^{1

2}, Weiguo Chu^{1

2}

Affiliations

¹ Nanofabrication Laboratory, CAS Key Laboratory for Nanophotonic Materials and Devices, CAS Key Laboratory for Nanosystems and Hierarchical Fabrication, CAS Center for Excellence in Nanoscience, National Center for Nanoscience and Technology, Beijing, 100190, China.
² Center of Materials Science and Optoelectronics Engineering, University of Chinese Academy of Sciences, Beijing, 100049, China.

Abstract

As an indispensable constituent of plasmonic materials/dielectrics for surface enhanced Raman scattering (SERS) effects, dielectrics play a key role in excitation and transmission of surface plasmons which however remain more elusive relative to plasmonic materials. Herein, different roles of vertical dielectric walls, and horizontal and vertical dielectric layers in SERS via 3D periodic plasmonic materials/dielectrics structures are studied. Surface plasmon polariton (SPP) interferences can be maximized within dielectric walls besieged by plasmonic layers at the wall thicknesses of integral multiple half-SPP_{plasmonic material-dielectric} -wavelength which effectively excites localized surface plasmon resonance to improve SERS effects by one order of magnitude compared to roughness and/or nanogaps only. The introduction of extra Au nanoparticles on thin dielectric layers can further enhance SERS effects only slightly. Thus, the designed Au/SiO₂ based SERS chips show an enhancement factor of 8.9 × 10¹⁰ , 265 times higher relative to the chips with far thinner SiO₂ walls. As many as 1200 chips are batch fabricated for a 4 in wafer using cost-effective nanoimprint lithography which can detect trace Hg ions as low as 1 ppt. This study demonstrates a complete generalized platform from design to low-cost batch-fabrication to applications for novel high performance SERS chips of any plasmonic materials/dielectrics.

Keywords: SERS chip design; batch fabrication; dielectric walls/layers; localized surface plasmon resonance (LSPR); surface plasmon polariton (SPP); trace detection.

Abstract

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