Highly Reliable Memory Operation of High-Density Three-Terminal Thyristor Random Access Memory

Hyangwoo Kim; Hyeonsu Cho; Hyeon-Tak Kwak; Myunghae Seo; Seungho Lee; Byoung Don Kong; Chang-Ki Baek

doi:10.1186/s11671-022-03667-7

Highly Reliable Memory Operation of High-Density Three-Terminal Thyristor Random Access Memory

Nanoscale Res Lett. 2022 Feb 23;17(1):28. doi: 10.1186/s11671-022-03667-7.

Authors

Hyangwoo Kim¹, Hyeonsu Cho², Hyeon-Tak Kwak³, Myunghae Seo⁴, Seungho Lee⁴, Byoung Don Kong³, Chang-Ki Baek^{1

3}

Affiliations

¹ Department of Convergence IT Engineering and Future IT Innovation Laboratory, Pohang University of Science and Technology (POSTECH), 37673, Pohang, South Korea.
² Department of Convergence IT Engineering and Future IT Innovation Laboratory, Pohang University of Science and Technology (POSTECH), 37673, Pohang, South Korea. hscho21@postech.ac.kr.
³ Department of Electrical Engineering, Pohang University of Science and Technology (POSTECH), 37673, Pohang, South Korea.
⁴ Future IT Innovation Laboratory, Pohang University of Science and Technology (POSTECH), 37673, Pohang, South Korea.

Abstract

Three-terminal (3-T) thyristor random-access memory is explored for a next-generation high-density nanoscale vertical cross-point array. The effects of standby voltages on the device are thoroughly investigated in terms of gate-cathode voltage (V_GC,ST) and anode-cathode voltage (V_AC,ST) in the standby state for superior data retention characteristics and low-power operation. The device with the optimized V_GC,ST of - 0.4 V and V_AC,ST of 0.6 V shows the continuous data retention capability without refresh operation with a low standby current of 1.14 pA. In addition, a memory array operation scheme of 3-T TRAM is proposed to address array disturbance issues. The presented array operation scheme can efficiently minimize program, erase and read disturbances on unselected cells by adjusting gate-cathode voltage. The standby voltage turns out to be beneficial to improve retention characteristics: over 10 s. With the proposed memory array operation, 3-T TRAM can provide excellent data retention characteristics and high-density memory configurations comparable with or surpass conventional dynamic random-access memory (DRAM) technology.

Keywords: Capacitorless 1T DRAM; Gated-thyristors; Memory array operation; Memory disturbance; Three-terminal TRAM.