Design and Implementation of Charge Pump Phase-Locked Loop Frequency Source Based on GaAs pHEMT Process

Ranran Zhao; Yuming Zhang; Hongliang Lv; Yue Wu

doi:10.3390/s22020504

Design and Implementation of Charge Pump Phase-Locked Loop Frequency Source Based on GaAs pHEMT Process

Sensors (Basel). 2022 Jan 10;22(2):504. doi: 10.3390/s22020504.

Authors

Ranran Zhao¹, Yuming Zhang¹, Hongliang Lv¹, Yue Wu¹

Affiliation

¹ Key Laboratory of Wide Band-Gap Semiconductor Materials and Devices, School of Microelectronics, Xidian University, Xi'an 710071, China.

Abstract

This paper realized a charge pump phase locked loop (CPPLL) frequency source circuit based on 0.15 μm Win GaAs pHEMT process. In this paper, an improved fully differential edge-triggered frequency discriminator (PFD) and an improved differential structure charge pump (CP) are proposed respectively. In addition, a low noise voltage-controlled oscillator (VCO) and a static 64:1 frequency divider is realized. Finally, the phase locked loop (PLL) is realized by cascading each module. Measurement results show that the output signal frequency of the proposed CPPLL is 3.584 GHz-4.021 GHz, the phase noise at the frequency offset of 1 MHz is -117.82 dBc/Hz, and the maximum output power is 4.34 dBm. The chip area is 2701 μm × 3381 μm, and the power consumption is 181 mw.

Keywords: GaAs pHEMT; charge pump phase-locked loop; low phase noise.