Real-time FPGA-based implementation of the AKAZE algorithm with nonlinear scale space generation using image partitioning

Parastoo Soleimani; David W Capson; Kin Fun Li

doi:10.1007/s11554-021-01089-9

Real-time FPGA-based implementation of the AKAZE algorithm with nonlinear scale space generation using image partitioning

J Real Time Image Process. 2021;18(6):2123-2134. doi: 10.1007/s11554-021-01089-9. Epub 2021 Mar 29.

Authors

Parastoo Soleimani¹, David W Capson¹, Kin Fun Li¹

Affiliation

¹ Department of Electrical and Computer Engineering, University of Victoria, Victoria, BC V8W 2Y2 Canada.

Abstract

The first step in a scale invariant image matching system is scale space generation. Nonlinear scale space generation algorithms such as AKAZE, reduce noise and distortion in different scales while retaining the borders and key-points of the image. An FPGA-based hardware architecture for AKAZE nonlinear scale space generation is proposed to speed up this algorithm for real-time applications. The three contributions of this work are (1) mapping the two passes of the AKAZE algorithm onto a hardware architecture that realizes parallel processing of multiple sections, (2) multi-scale line buffers which can be used for different scales, and (3) a time-sharing mechanism in the memory management unit to process multiple sections of the image in parallel. We propose a time-sharing mechanism for memory management to prevent artifacts as a result of separating the process of image partitioning. We also use approximations in the algorithm to make hardware implementation more efficient while maintaining the repeatability of the detection. A frame rate of 304 frames per second for a $1280 \times 768$ image resolution is achieved which is favorably faster in comparison with other work.

Keywords: AKAZE; FPGA; Hardware design; Image matching; Nonlinear scale space; Real-time.