Interlayer engineering for enhanced ferroelectric tunnel junction operations in HfO x-based metal-ferroelectric-insulator-semiconductor stack

Kyung Kyu Min; Junsu Yu; Yeonwoo Kim; Jong-Ho Lee; Daewoong Kwon; Byung-Gook Park

doi:10.1088/1361-6528/ac1e50

Interlayer engineering for enhanced ferroelectric tunnel junction operations in HfO _x-based metal-ferroelectric-insulator-semiconductor stack

Nanotechnology. 2021 Sep 16;32(49). doi: 10.1088/1361-6528/ac1e50.

Authors

Kyung Kyu Min^{1

2}, Junsu Yu¹, Yeonwoo Kim¹, Jong-Ho Lee¹, Daewoong Kwon³, Byung-Gook Park¹

Affiliations

¹ Inter-University Semiconductor Research Center, Department of Electrical and Computer Engineering, Seoul National University, Seoul 151-744, Republic of Korea.
² SK Hynix Inc., Icheon 17336, Republic of Korea.
³ Departmentof Electronic Engineering, Inha University, Incheon 22212, Republic of Korea.

PMID: 34404031
DOI: 10.1088/1361-6528/ac1e50

Abstract

Ferroelectric tunnel junction (FTJ) has been considered as a promising candidate for next-generation memory devices due to its non-destructive and low power operations. In this article, we demonstrate the interlayer (IL) engineering in the FTJs to boost device performances. Through the analysis on the material and electrical characteristics of the fabricated FTJs with engineered IL stacks, it is clearly found that the insertion of an Al₂O₃layer between the SiO₂insulator and the pure-HfO_xFE improves the read disturbance (2V_c = 2.2 V increased), the endurance characteristics (tenfold improvement), and the cell-to-cell TER variation simultaneously without the degradation of the ferroelectricity (less than 5%) and the polarization switching speeds through grain size modulation. Based on these investigations, the guidelines of IL engineering for low power ferroelectric devices were provided to obtain stable and fast memory operations.

Keywords: ferroelectric hafnium oxide (HfO x ); ferroelectric tunnel junction; interlayer engineering.