Terrace-confined guided growth of high-density ultrathin silicon nanowire array for large area electronics

Abstract

Ultrathin silicon nanowires (SiNWs) are ideal 1D channels to construct high performance nanoelectronics and sensors. We here report on a high-density catalytic growth of orderly ultrathin SiNWs, with diameter down toDnw=27±2nmand narrow NW-to-NW spacing of onlySnw ∼80 nm, without the use of high-resolution lithography. This has been accomplished via a terrace-confined strategy, where tiny indium (In) droplets move on sidewall terraces to absorb precoated amorphous Si layer as precursor and produce self-aligned SiNW array. It is found that, under proper parameter control, a tighter terrace-step confinement can help to scale the dimensions of the SiNW array down to the extremes that have not been reported before, while maintaining still a stable guiding growth over complex contours. Prototype SiNW field effect transistors demonstrate a highI_on/I_offcurrent ratio ∼10⁷, low leakage current of ∼0.3 pA and steep subthreshold swing of 220 mV dec^-1. These results highlight the unexplored potential of catalytic growth in advanced nanostructure fabrication that is highly relevant for scalable SiNW logic and sensor applications.

Keywords: field effect transistors; guided growth control; in-plane solid−liquid−solid mechanism; silicon nanowires.