The detection of a high repetition rate weak signal is studied in this paper. Owing to the characteristics of the signal of interest, both high speed analog-to-digital converter (ADC) and low computational complexity data processing techniques are required for high speed real-time weak signal detection. In this paper, a novel field programmable gate array (FPGA) based high speed real-time periodic weak signal detection technique is presented. Cascaded comparators outside the FPGA and cascaded flip flops in the FPGA are used to implement a one-bit ADC, which performs quantization first followed by sampling. Based on this novel design, a time-interleaved structure with several sub-channels is further proposed to significantly improve the sampling rate of the one-bit ADC, which does not require calibration for offset, gain, and sample-time mismatches between sub-channels. Each sub-channel has a long-time coherent integration structure to coherently integrate the sampled one-bit data. A full layer clearance mechanism that only operates on specific bits of the integrated sums is proposed to overcome the influence of a noise baseline drift on the weak signal detection. Compared with the traditional adaptive threshold, this mechanism has a significantly lower computational complexity. A prototype with three sub-channels performing 1.5 Gs/s sampling is implemented to verify the proposed technique. The results obtained confirm its high sampling rate and noise baseline drift tolerance in weak signal detection.