Design, FPGA implementation and statistical analysis of a high-speed and low-area TRNG based on an AES s-box post-processing technique

Abstract

The statistical weakness problem occurring as a result of physical randomness is an important shortcoming of TRNGs. Post-processing techniques are generally used in the literature to overcome this shortcoming. In this study, the hardware implementation of Advanced Encryption Standard (AES) substitution box (s-box)-based novel post-processing technique is presented. The low-cost novel method is based on the substitution s-box transformations and can successfully remove the statistical weakness problem of TRNGs. The real-time verification of the proposed post-processing is done by applying ring oscillator (RO) based TRNG architecture in four different scenarios on Field Programmable Gate Array (FPGA) environment. Successful statistical results obtained from bias, correlation, entropy and NIST 800-22 tests confirm the usability of the proposed method for cryptographic purposes. The low area-energy requirement, practicality and compressionless properties of the post-processing provide better tradeoff for TRNG compared to known methods in the literature. For this reason, TRNG's performance is high. Furthermore, the presented study is important in demonstrating that s-boxes with good mathematical encryption properties can also be used for different cryptographic purposes.

Keywords: AES s-box; Jitter; Post-processing; Ring oscillators; TRNG.