A Low-Resources TDC for Multi-Channel Direct ToF Readout Based on a 28-nm FPGA

Mojtaba Parsakordasiabi; Ion Vornicu; Ángel Rodríguez-Vázquez; Ricardo Carmona-Galán

doi:10.3390/s21010308

A Low-Resources TDC for Multi-Channel Direct ToF Readout Based on a 28-nm FPGA

Sensors (Basel). 2021 Jan 5;21(1):308. doi: 10.3390/s21010308.

Authors

Mojtaba Parsakordasiabi¹, Ion Vornicu¹, Ángel Rodríguez-Vázquez¹, Ricardo Carmona-Galán¹

Affiliation

¹ Instituto de Microelectrónica de Sevilla, IMSE-CNM (CSIC-Universidad de Sevilla), Avda. Américo Vespucio s/n, Parque Científico y Tecnológico de La Cartuja, 41092 Seville, Spain.

Abstract

In this paper, we present a proposed field programmable gate array (FPGA)-based time-to-digital converter (TDC) architecture to achieve high performance with low usage of resources. This TDC can be employed for multi-channel direct Time-of-Flight (ToF) applications. The proposed architecture consists of a synchronizing input stage, a tuned tapped delay line (TDL), a combinatory encoder of ones and zeros counters, and an online calibration stage. The experimental results of the TDC in an Artix-7 FPGA show a differential non-linearity (DNL) in the range of [-0.953, 1.185] LSB, and an integral non-linearity (INL) within [-2.750, 1.238] LSB. The measured LSB size and precision are 22.2 ps and 26.04 ps, respectively. Moreover, the proposed architecture requires low FPGA resources.

Keywords: field programmable gate array (FPGA); multichannel TDCs; single-photon avalanche diode (SPAD); tapped-delay-line (TDL); thermometer-to-binary (T2B) encoder; time-of-flight (ToF); time-to-digital converter (TDC).

Abstract

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