Special radiation-hard and ultralow-power complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) are used in the fields of deep space, nuclear energy, and medical X-ray imaging. In this work, we first constructed radiation-hard, repairable, and sub-1 V-driven printed hybrid CMOS field-effect transistors (FETs) and ICs, which integrate printed carbon nanotube (CNT) (band gap ∼ 0.65 eV) p-type FETs and indium oxide (In2O3) (band gap ∼3.64 eV) n-type FETs on glass substrates using a printed PS-PMMA/[EMIM][TFSI] mixture as the gate dielectric layer. The PS-PMMA/[EMIM][TFSI] mixture gate dielectric layer not only lowered the supply voltage (VDD) by providing ultrahigh gate efficiency but also improved the anti-irradiation ability of the hybrid CMOS FETs and ICs. Specifically, the hybrid CMOS inverters exhibited rail-to-rail output with a high voltage gain and high noise margins at a low VDD that could be scaled down to 0.4 V. Furthermore, the hybrid CMOS FETs and ICs showed excellent radiation hardness, that is, withstanding a 3 Mrad (Si) total irradiation dose (TID) at a dose rate of 560 rad s-1 (Si), which is an exceptional result for CMOS transistors and ICs. Furthermore, the radiation-damaged CMOS FETs could be fully recovered by removing and reprinting the PS-PMMA/[EMIM][TFSI] mixture gate dielectric layer, indicating the ability to repair irradiation damage. This work provides an in-space IC fabrication technology.
Keywords: PS-PMMA/[EMIM][TFSI] mixture; carbon nanotube; hybrid CMOS ICs; indium oxide; inkjet printing; radiation hardness.