Fixed Pattern Noise Reduction and Linearity Improvement in Time-Mode CMOS Image Sensors

Miron Kłosowski; Yichuang Sun

doi:10.3390/s20205921

Fixed Pattern Noise Reduction and Linearity Improvement in Time-Mode CMOS Image Sensors

Sensors (Basel). 2020 Oct 20;20(20):5921. doi: 10.3390/s20205921.

Authors

Miron Kłosowski¹, Yichuang Sun²

Affiliations

¹ Faculty of Electronics, Telecommunications and Informatics, Gdańsk University of Technology, 11/12 Gabriela Narutowicza Street, 80-233 Gdańsk, Poland.
² School of Engineering and Computer Science, University of Hertfordshire, Hatfield, Herts AL10 9AB, UK.

Abstract

In the paper, a digital clock stopping technique for gain and offset correction in time-mode analog-to-digital converters (ADCs) has been proposed. The technique is dedicated to imagers with massively parallel image acquisition working in the time mode where compensation of dark signal non-uniformity (DSNU) as well as photo-response non-uniformity (PRNU) is critical. Fixed pattern noise (FPN) reduction has been experimentally validated using 128-pixel CMOS imager. The reduction of the PRNU to about 0.5 LSB has been achieved. Linearity improvement technique has also been proposed, which allows for integral nonlinearity (INL) reduction to about 0.5 LSB. Measurements confirm the proposed approach.

Keywords: fixed pattern noise; gain correction; image sensor; integral nonlinearity correction; offset correction; time-mode ADC.

Grants and funding

2016/23/B/ST7/03733/Narodowe Centrum Nauki