In this article, by choosing and optimizing suitable structure in each stage, we have designed a multi-purpose low noise chopper amplifier. The proposed neural chopper amplifier with high CMRR and PSRR is suitable for EEG, LFP and AP signals while it has a low NEF. In order to minimize the noise and increase the bandwidth, a single stage current reuse amplifier with pseudo-resistor common-mode feedback is chosen, while a simple fully differential amplifier is implemented at the second stage to provide high swing. A DC servo loop with an active RC integrator is designed to block the DC offset of electrodes and a positive feedback loop is used to increase the input impedance. Finally, an area and power-efficient ripple reduction technique and chopping spike filter are used in order to have a clear signal. The designed circuit is simulated in a commercially available 0.18 μm CMOS technology. 3.7 μA current is drawn from a ±0.6V supply. The total bandwidth is from 50 mHz to 10 kHz while the total inputreferred noise in this bandwidth is 2.9 μVrms and the mid-band gain is about 40 dB. The designed amplifier can tolerate up to 60 mV DC electrode offset and the amplifier's input impedance with positive feedback loop is 17 MΩ while the chopping frequency is 20 kHz. With the designed ripple reduction, there is just a negligible peak in the input-referred noise due to upmodulated noise at chopping frequency. In order to prove the performance of the designed circuit, 500 Monte Carlo analysis is done for process and mismatch. The mean value for CMRR and PSRR are 94 and 80 dB, respectively.