Single-Grain Gate-All-Around Si Nanowire FET Using Low-Thermal-Budget Processes for Monolithic Three-Dimensional Integrated Circuits

Tung-Ying Hsieh; Ping-Yi Hsieh; Chih-Chao Yang; Chang-Hong Shen; Jia-Min Shieh; Wen-Kuan Yeh; Meng-Chyi Wu

doi:10.3390/mi11080741

Single-Grain Gate-All-Around Si Nanowire FET Using Low-Thermal-Budget Processes for Monolithic Three-Dimensional Integrated Circuits

Micromachines (Basel). 2020 Jul 30;11(8):741. doi: 10.3390/mi11080741.

Authors

Tung-Ying Hsieh^{1

2}, Ping-Yi Hsieh³, Chih-Chao Yang³, Chang-Hong Shen³, Jia-Min Shieh³, Wen-Kuan Yeh³, Meng-Chyi Wu¹

Affiliations

¹ Institute of Electronics Engineering, National Tsing Hua University, Hsinchu 30013, Taiwan.
² National Applied Research Laboratories, 3F, No. 106, Ho Ping E. Rd., Sec. 2, Taipei City 10622, Taiwan.
³ Taiwan Semiconductor Research Institute, No.26, Prosperity Road 1, Hsinchu 30013, Taiwan.

Abstract

We introduce a single-grain gate-all-around (GAA) Si nanowire (NW) FET using the location-controlled-grain technique and several innovative low-thermal budget processes, including green nanosecond laser crystallization, far-infrared laser annealing, and hybrid laser-assisted salicidation, that keep the substrate temperature (T_sub) lower than 400 °C for monolithic three-dimensional integrated circuits (3D-ICs). The detailed process verification of a low-defect GAA nanowire and electrical characteristics were investigated in this article. The GAA Si NW FETs, which were intentionally fabricated within the controlled Si grain, exhibit a steeper subthreshold swing (S.S.) of about 65 mV/dec., higher driving currents of 327 µA/µm (n-type) and 297 µA/µm (p-type) @ V_th ± 0.8 V, and higher I_on/I_off (>10⁵ @|V_d| = 1 V) and have a narrower electrical property distribution. In addition, the proposed Si NW FETs with a GAA structure were found to be less sensitive to V_th roll-off and S.S. degradation compared to the omega(Ω)-gate Si FETs. It enables ultrahigh-density sequentially stackable integrated circuits with superior performance and low power consumption for future mobile and neuromorphic applications.

Keywords: gate-all-around; laser activation; laser crystallization; laser-assisted salicidation; location-controlled-grain; low power consumption; low-thermal budget; monolithic 3D; nanowire FET.