Because nanoelectromechanical (NEM) memory switches generally have higher pull-in voltage (VPI) and lower reliability than CMOS devices, reducing VPI and maximum stress (σMAX) of NEM memory switches have been critical issues for the implementation of monolithic-3D (M3D) CMOS-NEM hybrid reconfigurable logic (RL) circuits. In this paper, a novel notched anchor design is proposed to reduce the VPI and σMAX of NEM memory switches. Moreover, the novel design has an advantage in terms of chip density over the conventional design under the same VPI condition. In the case of our proposed NEM memory switches, their anchors are placed in the vias of metal interconnection layers. Thus, even if notched patterns are formed on the anchors, it will be helpful to effectively increase beam length, which eventually lowers VPI and σMAX. In this manuscript, the proposed notched anchor design has been confirmed by finite-element-method (FEM) simulation. According to the simulation results, the proposed notched anchor design lowers VPI by ~23% and σMAX by ~24%.