ASIC modelling of SENSE for parallel MRI

Abstract

Magnetic Resonance Imaging (MRI) is widely used in medical diagnostics and image reconstruction is a vital part of MRI systems. In Parallel MRI (pMRI), imaging process is accelerated by acquiring less data (undersampled) using multiple receiver coils and offline reconstruction algorithms are applied to reconstruct the fully sampled image. In this research, an Application Specific Integrated Circuits (ASIC) model of SENSE (a pMRI algorithm) is presented which reconstructs the image from the undersampled data right on the data acquisition module of the scanner. The proposed ASIC HDL architecture is compared with SENSE reconstruction model implemented on FPGAs, Multi-core CPU and Graphics Processing Units. The proposed architecture is validated using simulated brain data with 8-channel receiver coils and a human cardiac dataset with 20-channel receiver coils. The quality of the reconstructed images is analyzed using Artifact Power (0.0098), Peak Signal-to-Noise Ratio (53.4) and Structured Similarity Index (0.871) which validate the quality of the reconstructed images using the proposed design. The results show that the proposed ASIC HDL SENSE reconstruction model is ∼8000 times faster as compared to the multi-core CPU reconstruction, ∼700 times faster than the GPU implementation and ∼16 times faster as compared to the FPGA reconstruction model. The proposed architecture is suitable for image reconstruction right on the data acquisition system of the scanner and will open new ways for faster image reconstruction on portable MRI scanners.

Keywords: ASIC modelling; FPGA; MRI reconstruction; Parallel MRI; Parallel computing.