Vertical Tunnel Field-Effect Transistor with Polysilicon Layer

Won Joo Lee; Hui Tae Kwon; Hyun-Seok Choi; Daehoon Wee; Yu Jeong Park; Boram Kim; Yoon Kim

doi:10.1166/jnn.2019.17111

Vertical Tunnel Field-Effect Transistor with Polysilicon Layer

J Nanosci Nanotechnol. 2019 Oct 1;19(10):6722-6726. doi: 10.1166/jnn.2019.17111.

Authors

Won Joo Lee¹, Hui Tae Kwon¹, Hyun-Seok Choi¹, Daehoon Wee¹, Yu Jeong Park¹, Boram Kim¹, Yoon Kim²

Affiliations

¹ Department of Nanoenergy Engineering, BK21 Plus Nanoconvergence Technology Division, Pusan National University, Busan, 46241, Korea.
² School of Electrical and Computer Engineering, University of Seoul, Seoul, 02504, Korea.

PMID: 31027017
DOI: 10.1166/jnn.2019.17111

Abstract

In this paper, a novel structure of tunnel field-effect transistors (TFETs) is proposed. The proposed device has an intrinsic polysilicon layer located in the overlap region between the source and the gate, which can increase the tunneling area and overcome the low ON-current drawback of the conventional TFET. The advantages of the proposed device are proven by using technology computeraided design (TCAD) simulation. It exhibits more than 50 higher on-current (I_ON) of 0.13 μA/μm and lower subthreshold swing (SS) of 53 mV/dec than a conventional planar TFET. In addition, the effect of some device parameters on the device performance has been investigated.