Variability-Aware Simulation Strategy for Gate-All-Around Vertical Field Effect Transistor

Kyul Ko; Myounggon Kang; Jongwook Jeon; Hyungcheol Shin

doi:10.1166/jnn.2019.17105

Variability-Aware Simulation Strategy for Gate-All-Around Vertical Field Effect Transistor

J Nanosci Nanotechnol. 2019 Oct 1;19(10):6715-6721. doi: 10.1166/jnn.2019.17105.

Authors

Kyul Ko¹, Myounggon Kang², Jongwook Jeon³, Hyungcheol Shin¹

Affiliations

¹ Inter University Semiconductor Research Center (ISRC) and School of Electrical Engineering and Computer Science, Seoul National University, Seoul 151-744, Korea.
² Department of Electronics Engineering, Korea National University of Transportation, Chungju-City 151-742, Korea.
³ Department of Electronics Engineering, Konkuk University, Seoul 05029, Korea.

PMID: 31027016
DOI: 10.1166/jnn.2019.17105

Abstract

In this work, the work function variation (WFV) and global variability (GV) sources on 5 nm node gate-all-around (GAA) silicon vertical field-effect transistor (VFET) devices are studied through technology computer-aided design (TCAD) simulations and spice simulation based on BSIM-CMG model. Compared to conventional lateral FET devices, VFETs can increase the gate area effectively while minimizing the loss of layout area due to their structural characteristics. Considering VFET devices below 5 nm node, an expansion of the gate area of the device reduces the influence of WFV. However, the effect of GV is exacerbated by weakening gate controllability. In order to analyze the exact variability issues, it is necessary to consider not only the influence by the WFV but also the influence by the GV. Therefore, we propose accurate guideline by analyzing the integrated variability issues in a various VFET device structures in a single device and a 6-T SRAM bit cells.