Improving ESD Protection Robustness Using SiGe Source/Drain Regions in Tunnel FET

Micromachines (Basel). 2018 Dec 12;9(12):657. doi: 10.3390/mi9120657.

Abstract

Currently, a tunnel field-effect transistor (TFET) is being considered as a suitable electrostatic discharge (ESD) protection device in advanced technology. In addition, silicon-germanium (SiGe) engineering is shown to improve the performance of TFET-based ESD protection devices. In this paper, a new TFET with SiGe source/drain (S/D) regions is proposed, and its ESD characteristics are evaluated using technology computer aided design (TCAD) simulations. Under a transmission line pulsing (TLP) stressing condition, the triggering voltage of the SiGe S/D TFET is reduced by 35% and the failure current is increased by 17% in comparison with the conventional Si S/D TFET. Physical insights relevant to the ESD enhancement of the SiGe S/D TFET are provided and discussed.

Keywords: Silicon-Germanium source/drain (SiGe S/D); band-to-band tunneling (BTBT); electrostatic discharge (ESD); technology computer aided design (TCAD); tunnel field-effect transistor (TFET).