Monolithic Low Noise and Low Zero-g Offset CMOS/MEMS Accelerometer Readout Scheme

Yu-Sian Liu; Kuei-Ann Wen

doi:10.3390/mi9120637

Monolithic Low Noise and Low Zero-g Offset CMOS/MEMS Accelerometer Readout Scheme

Micromachines (Basel). 2018 Nov 30;9(12):637. doi: 10.3390/mi9120637.

Authors

Yu-Sian Liu¹, Kuei-Ann Wen²

Affiliations

¹ Institute of Electronic Engineering, National Chiao Tung University, Hsinchu 300, Taiwan. thomas.ee02g@nctu.edu.tw.
² Institute of Electronic Engineering, National Chiao Tung University, Hsinchu 300, Taiwan. stellawen@mail.nctu.edu.tw.

Abstract

A monolithic low noise and low zero-g offset CMOS/MEMS accelerometer and readout scheme in standard 0.18 μm CMOS mixed signal UMC process is presented. The low noise chopper architecture and telescopic topology is developed to achieve low noise. The experiments show noise floor is 421.70 μg/√Hz. The whole system has 470 mV/g sensitivity. The power consumption is about 1.67 mW. The zero-g trimming circuit reduces the offset from 1242.63 mg to 2.30 mg.

Keywords: Accelerometer readout; low noise; low zero-g offset.