With the process nodes extending to sub-10-nm in advanced semiconductor manufacturing, the overlay requirements keep progressively scaling down, which makes it very important to measure overlay precisely for monitoring on-product performance. The overlay mark being asymmetrical when generated via the lithography process, this asymmetry will be slightly variated even in the same process or same lot, and it will bring overlay measurement error. In general, the wafer alignment data are used for correcting this overlay measurement error, utilizing its wavelengths and polarizations dependence. However, there is a residual error that cannot be removed because the structures of the wafer alignment mark and overlay mark are different and are affected by the process differently. In this paper, a new method is proposed for calibrating the overlay measurement error introduced by the asymmetric mark, which is based on the relationship between measurement data of the overlay mark and the single layer mark. The validity is verified by simulation with different types of asymmetric mark. It is very useful for improving overlay measurement accuracy and for understanding how the overlay measurement error is affected by the asymmetric mark.