In this research, a passivated methodology was proposed for achieving good electrical characteristics for back-channel-etch (BCE) typed amorphous Si-Sn-O thin film transistors (a-STO TFTs). This methodology implied that the thermal annealing (i.e., pre-annealing) should be carried out before deposition of a SiOx passivation layer. The pre-annealing played an important role in affecting device performance, which did get rid of the contamination of the lithography process. Simultaneously, the acceptor-like sub-gap density of states (DOS) of devices was extracted for further understanding the reason for improving device performance. It found that the SiOx layer could reduce DOS of the device and successfully protect the device from surroundings. Finally, a-STO TFT applied with this passivated methodology could possess good electrical properties including a saturation mobility of 4.2 ± 0.2 cm²/V s, a low threshold voltage of 0.00 V, a large on/off current ratio of 6.94 × 10⁸, and a steep subthreshold swing of 0.23 V/decade. The threshold voltage slightly shifted under bias stresses and recovered itself to its initial state without any annealing procedure, which was attributed to the charge trapping in the bulk dielectric layers or interface. The results of this study indicate that a-STO TFT could be a robust candidate for realizing a large-size and high-resolution display.
Keywords: SiOx passivation layer; amorphous Si-Sn-O semiconductor; density of states; stability.